RISC-V core on FPGA
A minimal in-order RISC-V processor written in Verilog, with a 5-stage pipeline, UART debug output, and synthesized/running on an FPGA dev board.
01 / about
I'm a computer-engineering-focused engineer working at the intersection of software and silicon. I like understanding systems from the register transfer level all the way up to the application running on top of them.
On the embedded side I write firmware that talks directly to the metal — UARTs, SPI buses, timers and interrupts. On the digital design side I use Verilog to describe, simulate and synthesize hardware on FPGAs, closing timing and verifying behavior before it ever ships.
Whether it's a sensor node in the field or a custom core on a fabric, my goal is the same: hardware-software co-design that's correct, efficient and reliable.
Currently focused on
- FPGA digital design & RTL in Verilog
- Embedded C firmware for MCUs
- Timing closure & logic synthesis
- UVVM / testbench verification
02 / skills & tools
Digital Design
- Verilog
- SystemVerilog
- RTL
- FSM
- Timing closure
- Logic synthesis
FPGA Toolchains
- Xilinx Vivado
- Intel Quartus
- Lattice iCEcube
- yosys / nextpnr
Embedded
- C
- C++
- ARM Cortex-M
- AVR
- UART
- SPI
- I2C
- Timers & interrupts
Verification & Tooling
- Testbenches
- Simulation
- Git
- Linux
- Make
- GNU toolchain
// Swap these chips for the exact tools and skills you use —
edit the lists in index.html.
03 / selected projects
UART IP block
Synthesizable UART transmitter/receiver with configurable baud rate, FIFO buffering and a clean AXI-style interface for easy SoC integration.
Sensor node firmware
Low-power embedded C firmware collecting sensor data over SPI and streaming it over a wireless link, with deep-sleep power management.
Verilog testbench suite
A parameterized, self-checking testbench environment for block-level verification of RTL modules, with waveform dumping and assertion checks.
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